Article ID: 000075003 Content Type: Product Information & Documentation Last Reviewed: 07/04/2019

How can I perform IBIS simulation of configuration pins for Cyclone® V and Arria® V GX devices?


  • Intel® Quartus® Prime Pro Edition

    To simulate configuration pins using IBIS models for Cyclone® V devices, follow the steps below  to choose the appropriate IBIS model. The flow is similar for Arria® V GX devices.

    1) Pick the configuration pin that you wish to simulate from Table 7-4: I/O Standards and Drive Strength for Configuration Pins in Cyclone V Device Handbook

    2) Narrow down the model with cyclone5 models.xls  file available from IBIS MODELS for Intel Devices based on the rules in the example below.

    For example, for the DCLK pin, the table shows the IO standard as 3.0 V LVTTL and 12mA

    Apply the following rules when choosing the IBIS model

    · Without suffix _p => stands for clamping diode on (which is not used for configuration pins)

    · Without s0 = slow slew rate (for configuration pins, the default is fast slew rate)

    Therefore you end-up with lvttl30(crnio/crpio/ctnio/ctpio)_d12s1.

    The above rules are applicable for all other configuration pins.

    Related Products

    This article applies to 2 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V GX FPGA



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