100GbE IP Core Might Not Maintain Average Minimum Inter-Packet Gap of 12

If a 100GbE IP core variation has the following two register settings

• TX CRC insertion turned on (bit [0] of the CRC_CONFIG register at offset 0x123 is set)
• Enable TX preamble pass-through turned on (bit [0] of the Preamble Pass-Through Configuration register at offset 0x125 is set)

the IP core might not maintain an average minimum inter-packet gap (IPG) of 12 during 100% bandwidth traffic.

This issue does not occur in 40GbE IP core variations.

This issue has no workaround. You must either redesign to remove the need for one or both of the two features, or you must tolerate the IPG non-compliance during 100% bandwidth traffic.

Another option is to use the Low Latency 40-100GbE IP core in your design instead of the 40-100GbE IP core. The Low Latency 100GbE IP core is tested for compliance with the Ethernet requirement of an average minimum IPG of 12 when these two features are turned on.

This issue will be fixed in a future version of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.