Article ID: 000074986 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there an issue with "Enable Auto Power Down" option in DDR2 and DDR3 SDRAM UniPHY based controller generated in Quartus II software version 11.0 and 11.0SP1?



Yes, there is an issue with the "Enable Auto Power Down" option in the DDR2 and DDR3 SDRAM UniPHY based controller IP version 11.0 and 11.0SP1.

When the option is enabled, after user specified cycles (Auto Power Down Cycles) of idle time, the controller automatically places the memory into power-down mode. When the option is disabled, the controller never places the memory into power down.

When you want the "Enable Auto Power Down" option enabled, you select the option in the Megawizard and also specify “Auto Power Down Cycles”. When you have the option enabled, the local_powerdn_ack port is not exported to the top as it should be. You should export the signals local_powerdn_req and local_powerdn_ack to the top level and tie local_powerdn_req to low as it is not used by the IP.

When you do not want to enable this option, you do not select "Enable Auto Power Down" option. With the current version of the IP, the port generation and export is reversed for the "Enable Auto Power Down" option. When you have the option disabled, the functionality is disabled but the ports local_powerdn_req and local_powerdn_ack are exported to the top level. Connect the local_powerdn_req to low and you can ignore local_powerdn_ack signal.

This issue will be fixed in the future version of the Quartus® II software and IP.

Related Products

This article applies to 7 products

Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® IV GX FPGA