Article ID: 000074977 Content Type: Troubleshooting Last Reviewed: 07/04/2016

DisplayPort HBR TX Native PHY Preset Not Aligned with Design Example

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The DisplayPort TX Native PHY preset for HBR data rate is not aligned with the DisplayPort design example settings. The Native PHY preset configures the TX local clock division factor to 2, but in the design example settings, the expected clock division factor is 1. This issue causes the DisplayPort to transmit the serial data in the wrong clock rate.

    Resolution

    To work around this issue, change the Native PHY TX local clock division factor from 2 to 1.

    This issue is fixed in version 15.1 Update 2 of the DisplayPort IP core.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices