Why TimeQuest Timing Analyzer might improperly report setup violations?

Description In the XAUI PHY version 10.1 and earlier, during timing analysis of a soft XAUI PHY MegaCore® function, the TimeQuest Timing Analyzer might report setup violations within the mgmt_clk_clk domain and between the gmt_clk_clk and another clock domain. The TimeQuest Timing Analyzer might also report hold time violations.

Affected Configurations

This issue affects the soft IP implementation of the XAUI PHY IP core in Stratix® V devices.

Solution Status

This issue is fixed in the XAUI PHY MegaCore function version 10.1 SP1.

Resolution

The majority of paths that show violations are between asynchronous signals and consequently are false timing paths. In addition, because there is no relationship between the mgmt_clk_clk and refclk_clk, these timing violations represent false paths. To eliminate timing errors for these false paths, you can add the following statements  to your Synopsis Design Constraints File (.sdc).

set_false_path -from [get_clocks refclk_clk] -to [get_clocks mgmt_clk_clk]

set_false_path -from [get_clocks mgmt_clk_clk] -to [get_clocks refclk_clk]

set_false_path -from [get_clocks {*|alt_pma_0|alt_pma_sv_inst|sv_xcvr_generic_inst|channel_tx[0].duplex_pcs|ch[0].rx_pcs|clocktopld}] -to [get_clocks mgmt_clk_clk]

The timing paths in the mgmt_clk_clk domain, in the following code,  are not false paths; however, you can ignore these errors or other errors that are within the soft XAUI IP core.

1. From Node top:i|top_0002:top_inst|top_alt_xcvr_reconfig_0:alt_xcvr_reconfig_0|alt_xcvr_reconfig_analog:analog_reconfig_instance|alt_xcvr_reconfig_analog_sv:reconfig_analog_sv|chnl_addr_reg[7]

; To Node ; top:i|top_0002:top_inst|top_alt_xcvr_reconfig_0:alt_xcvr_reconfig_0|alt_xcvr_reconfig_analog:analog_reconfig_instance|alt_xcvr_reconfig_analog_sv:reconfig_analog_sv|analog_reconfig_readdata[2] ;

2. From Node ; top:i|top_0002:top_inst|top_alt_xcvr_reconfig_0:alt_xcvr_reconfig_0|alt_xcvr_reconfig_analog:analog_reconfig_instance|alt_xcvr_reconfig_analog_sv:reconfig_analog_sv|chnl_addr_reg[7] ;

; To Node ; top:i|top_0002:top_inst|top_alt_xcvr_reconfig_0:alt_xcvr_reconfig_0|alt_xcvr_reconfig_analog:analog_reconfig_instance|alt_xcvr_reconfig_analog_sv:reconfig_analog_sv|analog_reconfig_readdata[3] ;

Finally, the soft IP implementation of the XAUI PHY might show hold time violations which may also be safely ignored.

No workaround is required.