** Warning: ../ip_ad_lvds/altera_lvds_core14_181/sim/ip_ad_lvds_altera_lvds_core14_181_ibrwinq.sv(1): (vlog13233) Design unit "ip_ad_lvds_altera_lvds_core14_181_ibrwinq" already exists and will be overwritten. Overwriting a VHDL entity with a Verilog modu

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1,  you may see the following warning (as shown below) in the ModelSim* GUI when using Intel® Stratix® 10 LVDS SERDES IP: 

** Warning: ../ip_ad_lvds/altera_lvds_core14_181/sim/ip_ad_lvds_altera_lvds_core14_181_ibrwinq.sv(1): (vlog13233) Design unit "ip_ad_lvds_altera_lvds_core14_181_ibrwinq" already exists and will be overwritten. Overwriting a VHDL entity with a Verilog module.

There is no workaround for this issue.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.