Article ID: 000074930 Content Type: Troubleshooting Last Reviewed: 02/27/2014

Rule C105: Clock signal should be a global signal

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see the following warnings when running the Design Assistant tool in Quartus II software on your compiled HPS design.

Rule C105: Clock signal should be a global signal ;            <hierarchy>|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk 

Rule C105: Clock signal should be a global signal ; <hierarchy>|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk

These warnings are expected and can be safely ignored.

Resolution

 

Related Products

This article applies to 6 products

Cyclone® V ST SoC FPGA
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Cyclone® V SX SoC FPGA

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