Article ID: 000074909 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Why does DDR HP Controller Simulation fails when using CAS latency of 2.0 or 2.5?


  • Simulation
    Description For DDR CAS latency 2.0 and 2.5 designs to sequencer is operating close to the supported minimum latency. There is a known issue with a VHDL generated sequencer block which results in a failure in simulation whereas a Verilog version of the same design would pass. The issue is due to delta cycle delays on a clock net. To fix this issue the following steps should be taken:

    1) Open the <variation_name>_phy.vho file in the project directory

    2) Search for the altsyncram instantiation for the postamble block (this can be done by searching for " altsyncram" - note the white space). This should be the altsyncram component with a label which includes the word "postamble".

    3) Search for the signal which is attached to the clock1 port (which is named similar to the name below) to find the point in the design where this signal is assigned to (This port is typically around line 4043).


    4) Change the assignment to the that shown below. The signal inside not(..) should be the same as the signal on clock0 port of a second instance of the altsyncram component which is associated to the read datapath (with "read_dp" in the label).

    wire_<variation_name>_phy_<variation_name>_phy_alt_mem_phy_sii_<variation_name>_phy_alt_mem_phy_sii_inst_<variation_name>_phy_alt_mem_phy_postamble_sii_poa_altsyncram_half_rate_ram_gen_altsyncram_inst_19557_clock1 <= not (wire_<variation_name>_phy_<variation_name>_phy_alt_mem_phy_sii_<variation_name>_phy_alt_mem_phy_sii_inst_<variation_name>_phy_alt_mem_phy_clk_reset_sii_clk_<variation_name>_phy_alt_mem_phy_pll_sii_pll_19462_c4);

    Note: this step removes a delta delay for simulation but leaves the code unchanged. The right hand side of the assignment above is taken as the right hand side of the assignment to the signal which is previously assigned to the "wire_<variation_name>_phy_<variation_name>_phy_alt_mem_phy_sii_<variation_name>_phy_alt_mem_phy_sii_inst_<variation_name>_phy_alt_mem_phy_postamble_sii_poa_altsyncram_half_rate_ram_gen_altsyncram_inst_19557_clock1" signal.

    5) If the <variation_name>_phy component is recompiled in your simulator the design should now pass.

    Related Products

    This article applies to 3 products

    Arria® GX FPGA
    Stratix® II GX FPGA
    Stratix® II FPGAs