Article ID: 000074903 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does PLL reconfiguration give me the wrong results on my clock outputs?


Description Beginning in Quartus II software version 4.2, the fitter may route PLL output clocks from different counters than specified by the designer to improve routing. For example, a clock that is connected to port C0 in a design may not be connected to the C0 counter (it may be routed to the C2 counter because that may improve the ability to route the design). In that case, a PLL scan chain file used for PLL reconfiguration may not target the correct counter. The file may reconfigure the C0 counter as the designer had planned, but the C2 counter is the one connected to the output clock. The C2 clock will then be reconfigured with different settings than intended, and thus, unpredictable results may occur.

Set the PRESERVE_PLL_COUNTER_ORDER logic option to ON for that PLL. Alternatively, the designer can check the PLL usage in the compilation report file and adjust the reconfiguration scan chain file to target the counters selected by Quartus II.

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Stratix® II FPGAs