Article ID: 000074887 Content Type: Error Messages Last Reviewed: 12/15/2022

Error (15847): Illegal value "none" for ena_register_mode parameter in Clock Control Block "altclk_ext_CIVE_altclkctrl_0:xaltclk_ext_CIVE_altclkctrl_0_inst|altclk_ext_CIVE_altclkctrl_0_sub:altclk_ext_CIVE_altclkctrl_0_sub_component|clkctrl1"

Environment

  • Intel® Quartus® Prime Pro Edition
  • ALTCLKCTRL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error in the Intel® Quartus® Prime Standard Software version 16.1 when compiling a Cyclone® IV design with an instance of the Clock Control Block (ALTCLKCTRL) IP with the "ena" port enabled.

    Error (15847): Illegal value "none" for ena_register_mode parameter in Clock Control Block "altclk_ext_CIVE_altclkctrl_0:xaltclk_ext_CIVE_altclkctrl_0_inst|altclk_ext_CIVE_altclkctrl_0_sub:altclk_ext_CIVE_altclkctrl_0_sub_component|clkctrl1" -- value must be "double register" when the ena input is used and the clock type is "External Clock Output"

    Resolution

    To work around this issue, manually change the register_ena_mode in the auto-generated RTL from "none" to "double register." 

    This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 17.1.

    Related Products

    This article applies to 1 products

    Cyclone® IV FPGAs

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