Article ID: 000074884 Content Type: Troubleshooting Last Reviewed: 11/21/2017

Can GPIO pins being place at the I/O bank 1B when the ADC block enabled for Max 10 device?

Environment

  • Quartus® II Subscription Edition
  • Modular Dual ADC core Intel® FPGA IP
  • Modular ADC core Intel® FPGA IP
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    Description

    Yes, the GPIO pins can be placed at I/O bank 1B if you are not receive the critical warning message (16248) for Max® 10 device. Quartus® Prime software uses physics-based rules to define the number of I/Os allowed in I/O bank 1B based on the I/O’s drive strength. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance. The critical warning message (16248) will generate when the noise generated by the GPIO pin exceed the noise threshold.

    The physics-based rules are available for the following devices starting from these Quartus® Prime software versions:

    • From Quartus® Prime Software v14.1— Max® 10 10M04, 10M08, 10M40, and 10M50 devices.

    • From Quartus® Prime Software v15.0.1— Max® 10 10M02, 10M16, and 10M25 devices.

     

    Prior to physics-based rules implementation, Quartus® Prime Software used the geometric rules which meant I/O bank 1B cannot be used as GPIO pins when the ADC block enabled. 

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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