When using the Parallel Flash Loader Intel® FPGA IP, the timing constraints for fpga_data and fpga_dclk are described in Constraining PFL Timing in Parallel Flash Loader Intel® FPGA IP Core User Guide. However, the constraints in document version 2019.02.19 and earlier are not correct.
To properly constrain timing of fpga_data and fpga_dclk, use one of the following timing constraints depending on the ratio between input clock and DCLK output.
[ When ratio between input clock and DCLK output = 1 ]
# Create Clock
create_clock -name {pfl_clk} -period <pfl_clk period> -waveform { 0.000 <pfl_clk period>/2 } [get_ports {pfl_clk}]
# Create Generated Clock
create_generated_clock -name {fpga_dclk} -source [get_ports {pfl_clk}] -master_clock {pfl_clk} -invert [get_ports {fpga_dclk}]
# Set Output Delay
set_output_delay -add_delay -max -clock [get_clocks {fpga_dclk}] <Setup time constraint> [get_ports {fpga_data*}]
set_output_delay -add_delay -min -clock [get_clocks {fpga_dclk}] <Hold time constraint> [get_ports {fpga_data*}]
[ When ratio between input clock and DCLK output > 1 ]
# Create Clock
create_clock -name {pfl_clk} -period <pfl_clk period> -waveform { 0.000 <pfl_clk period>/2 } [get_ports {pfl_clk}]
# Create Generated Clock
create_generated_clock -name {<clock name of DCLK register output>} -source [get_ports {pfl_clk}] -divide_by <Ratio between input clock and DCLK output> -master_clock {pfl_clk} [get_registers {<DCLK register>} ]
create_generated_clock -name {<clock name of DCLK at fpga_dclk pin>} -source [get_registers {<DCLK register>}] -master_clock {<clock name of DCLK register output>} [get_ports {fpga_dclk}]
# Set Output Delay
set_output_delay -add_delay -max -clock [get_clocks {<clock name of DCLK at pin>}] -reference_pin [get_ports {fpga_dclk}] <Setup time constraint> [get_ports {fpga_data*}]
set_output_delay -add_delay -min -clock [get_clocks {<clock name of DCLK at pin>}] -reference_pin [get_ports {fpga_dclk}] <Hold time constraint> [get_ports {fpga_data*}]
# Set Multicycle Path
set_multicycle_path -setup -start -from [get_clocks {pfl_clk}] -to [get_clocks {<clock name of DCLK at pin>}] < Ratio between input clock and DCLK output>/2
set_multicycle_path -hold -start -from [get_clocks {pfl_clk}] -to [get_clocks {<clock name of DCLK at pin>}] <Ratio between input clock and DCLK output> -1
• In this examples, PFL Intel FPGA IP core’s port names are used.
• DCLK register is a register to divide pfl_clk. The register name is usually “fpga_dclk_reg”. You can find the register by tracing the source destination from fpga_dclk port using the Technology Map Viewer tool.
• Intel recommends to use Timing Analyzer GUI to validate the constratrains.
[Example]
• Condition
o pfl_clk period = 20ns (50MHz)
o Ratio between input clock and DCLK output = 2
• Timing constraints
# Create Clock
create_clock -name {pfl_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {pfl_clk}]
# Create Generated Clock
create_generated_clock -name {fpga_dclk_gen} -source [get_ports {pfl_clk}] -divide_by 2 -master_clock {pfl_clk} [get_registers {pfl:inst|altparallel_flash_loader:altparallel_flash_loader_component|alt_pfl:\PFL_CFI:pfl_cfi_inst|alt_pfl_cfg3:\CFG3:cfg|alt_pfl_cfg_fpga:alt_pfl_cfg_fpga|fpga_dclk_reg}]
create_generated_clock -name {fpga_dclk_pin} -source [get_registers {pfl_top:pfl_top_inst|altera_parallel_flash_loader:parallel_flash_loader_0|altparallel_flash_loader:altparallel_flash_loader_component|alt_pfl:\PFL_CFI:pfl_cfi_inst|alt_pfl_cfg3:\CFG3:cfg|alt_pfl_cfg_fpga:alt_pfl_cfg_fpga|fpga_dclk_reg}] -master_clock {fpga_dclk_gen} [get_ports {fpga_dclk}]
# Set Output Delay
set_output_delay -add_delay -max -clock [get_clocks {fpga_dclk_gen}] -reference_pin [get_ports {fpga_dclk}] 5.500 [get_ports {fpga_data*}]
set_output_delay -add_delay -min -clock [get_clocks {fpga_dclk_gen}] -reference_pin [get_ports {fpga_dclk}] -1.000 [get_ports {fpga_data*}]
# Set Multicycle Path
set_multicycle_path -setup -start -from [get_clocks {pfl_clk}] -to [get_clocks {fpga_dclk_pin}] 1
set_multicycle_path -hold -start -from [get_clocks {pfl_clk}] -to [get_clocks {fpga_dclk_pin}] 1