Article ID: 000074806 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How can I access the Stratix V ES device JTAG port on the Stratix V ES FPGA Development Kit using the FACTORY instruction?



The Stratix® V GX ES FPGA Development Kit contains a Stratix V ES device and MAX® V device in the JTAG chain. In order to issue the FACTORY instruction into the Stratix V ES device, the .jam file must be modified by changing the IRSCAN instruction to bypass the MAX V device. Since the MAX V is the second device in the JTAG chain, change the line from


IRSCAN 10, 81;




IRSCAN 20, ;


You can use this Jam STAPL file to issue the FACTORY instruction into the Stratix V ES device on the Stratix V GX ES FPGA development kit.



You must issue the JTAG FACTORY instruction after each power up because powering down and powering up the device puts the device back into secure mode. To issue the JTAG FACTORY instruction, follow these steps:


1. Before powering up the board, press the S2 button (pgm_load).


2. While pressing S2, power up the board and issue the FACTORY instruction by executing the .jam file using quartus_jli with the following command:


quartus_jli -c<cable> -aISSUE_FACTORY factory.jam


3. After step 2 is done, release the button S2.


4. You can now access the Stratix V ES device JTAG port.

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Stratix® V GX FPGA