When implementing Partial Reconfiguration (PR) on Intel® Arria® 10 AX016/AS016/AX032/AX032 devices, the generated Raw Binary File (rbf) size may differ a lot when constrained to different LogicLock positions in Chip Planner, even with the same LogicLock region size. For example, contraining a PR LogicLock region to the bottom in Chip Planner may cause the rbf file size to be 10 times larger than if constrained to the top in Chip Planner, consequently resulting in a longer PR configuration time.
This is expected behavior for Intel Arria 10 AX016/AS016/AX032/AS032 devices. When the PR LogicLock region is at the bottom of the device, the generated rbf will include all frames from the top to the PR region, so it's expected to generate a much larger rbf file.
If sensitive to PR configuration time, constrain LogicLock regions to the top of the device to get a smaller rbf file.