Article ID: 000074772 Content Type: Product Information & Documentation Last Reviewed: 08/13/2012

How should I use the four dedicated PCI Express nPERST* pins on Stratix V devices?


  • PCI Express

    The four dedicated PCI® Express nPERST* pins found on Stratix® V devices should be used when implementing the Hard IP (HIP) for PCI Express.

    Only one nPERST pin is used per PCIe HIP. Stratix V devices always have all four pins listed, even if the target device only has 1 or 2 PCIe HIPs. These pins are listed below.

    nPERSTL0 = Bottom Left PCIe HIP & CvP
    nPERSTL1 = Top Left PCIe HIP (When available)
    nPERSTR0 = Bottom Right PCIe HIP (When available)
    nPERSTR1 = Top Right PCIe HIP (When available)

    For maximum compatibility we recommend that the Bottom Left PCIe HP always be used first, as this is the only location that supports CvP (Configuration via Protocol - Over the PCIe link).

    For Example: When using the bottom left PCIe HIP location, simply connect nPERST from your PCIe slot directly to nPERSTL0 on the device, which equates to signal pcie_rstn on the IP instance.

    The dedicated nPERST pins may be driven by 3.3V regardless of the VCCIO voltage level of the bank without a level translator as long as the input signal meets the LVTTL VIH/VIL specification, and as long as it meets the overshoot specifications for 100% operation as defined in the "DC and Switching Characteristics for Stratix V Devices." chapter of the Stratix V handbook.

    Related Products

    This article applies to 3 products

    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA