Article ID: 000074768 Content Type: Troubleshooting Last Reviewed: 07/16/2013

Does the FFT MegaCore implement the Global Clock Enable feature for the Floating Point Variable Streaming?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The FFT MegaCore® does not implement the Global Clock Enable feature for the Floating Point variable streaming.   The following error messages will appear when both “Global Clock Enable” and  “Floating Point” are selected:

 

 

MegaCore Function Generation Error

IP Functional Simulation Model Creation Failed. The following error was returned:

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful, 1 error, 1 warning

  • This error message is given when generating the FFT MegaCore Functional Simulation Model

 

Error (12002): Port "clk_ena" does not exist in macrofunction "apn_fftfp_top_fft_130_inst"

  • This error message is given when the Quartus® II software performs Analysis & Synthesis

 

             

Resolution

This issue will be fixed in a future version of the Quartus II software.

Related Products

This article applies to 1 products

Intel® Programmable Devices