Article ID: 000074759 Content Type: Troubleshooting Last Reviewed: 09/12/2012

Why do rx_st_err signal continues to drive an unknown value ('X') during Stratix V PCIe core simulation?

Environment

    Quartus® II Subscription Edition
    Simulation
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to a bug in the Stratix V PCIe Hard IP core the rx_st_err signal is incorrectly assigned in the file "altpcie_sv_hip_ast_hwtcl.v".
Resolution

To workaround this issue open the file "altpcie_sv_hip_ast_hwtcl.v" then find and change the following line:
From:

   assign rx_st_err = |rx_st_err_int[3:0];

To:
   assign rx_st_err = rx_st_err_int[0];

This issue will be fixed in a future version of the Quartus® II software release.

Related Products

This article applies to 2 products

Stratix® V FPGAs
Stratix® V GX FPGA

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