Critical Issue
The issue is triggered when a user try to configure some IP which results in different port lists. In that case, Qsys Pro generates VHDL wrapper files under the same system generation directory.
For example, if add two reset_bridge
to a Qsys Pro system from the IP
catalog, and configure one to use reset request signal, and the other without using
reset request signal. When you choose “generate VHDL” for either synthesis or
simulation. You can find that there are two files generated under system generation
directory. When you try to compile it, you get the following error: VHDL use
clause error at
xxx: VHDL design library does
not contain primary unit
xxx.
Generate Verilog instead of VHDL.