Description
Due to a problem in the Quartus® II software versions 14.1 Update 1 and earlier, you might see this error when compiling an Intel® Arria® 10 FPGA design containing a Hard IP for PCI Express (PCIe) where logic is placed between the nPERST pin and the Hard IP for PCI Express (PCIe) Intel FPGA IP core.
Resolution
Remove any logic placed between the nPERST pin and the Hard IP for PCI Express (PCIe) Intel FPGA IP core as this is not supported.
This error message is scheduled to be improved in Quartus® II software v15.01.