Article ID: 000074716 Content Type: Troubleshooting Last Reviewed: 12/26/2014

Wrong Decoding of MISC1 in DisplayPort Receiver

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

When used in lane 1 configurations, the DisplayPort IP core receiver may produce wrong MISC1 data as part of the received MSA. The logical state of the 3D video qualifier may also be wrong.

This issue is fixed in version 14.1 of the DisplayPort IP core.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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