Article ID: 000074712 Content Type: Troubleshooting Last Reviewed: 02/05/2015

Why does a design with a TX and RX Soft-CDR LVDS SERDES assigned to the same bank in an Arria 10 device fail to fit?

Environment

  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Quartus® II Subscription Edition
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    Description

    Due to a bug in  the Quartus® II software, a design which has an Altera® LVDS SERDES IP core configured in TX mode and an Altera LVDS SERDES IP core configured in RX Soft-CDR mode assigned to the same IO bank in an Arria® 10 device will fail at the fitter stage.  This is because the PLL instances within the two IP cores will not be correctly merged by the Quartus II software and so different PLLs will be required for the different Altera LVDS SERDES IP cores.  Each I/O bank has only one I/O PLL though.

    This problem only affects the RX Soft-CDR configuration.  RX Non-DPA or RX DPA-FIFO configurations are not affected.

    Note that the Triple Speed Ethernet IP core uses Altera LVDS SERDES IP configured in RX Soft-CDR mode.

    Resolution

    A patch is available for version 14.0 Arria 10 Edition of the Quartus II software.

    This problem is scheduled to be fixed in a future release of the Quartus II software.

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