In Synopsys Design Constraint (SDC) format, constrain a divided-down clock generated from the falling edge of the source clock using the create_generated_clock with the -edges option. For example, if your design contains a register clkdiv that divides its input frequency by two based on the falling edge of the source clock, use the following command:
create_generated_clock -name clkdiv -source [get_pins {clkdiv|clk}] \
-edges {2 4 6} [get_pins {clkdiv|q}] .
This command generates a clock with edges at the second, fourth and sixth edges of the source clock, which correspond to the first falling edge, second falling edge and third falling edge, respectively.
Note that the -invert option of the create_generated_clock command inverts the generated clock waveform, not the source clock. The -invert option does not affect whether the generated waveform is relative to the rising edge or the falling edge of the source clock.