Article ID: 000074666 Content Type: Troubleshooting Last Reviewed: 07/04/2019

What can cause the Intel® Stratix® 10 Serial Flash Mailbox Client IP to stop functioning?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Altera S10 Mailbox Client Core
  • Mailbox Client Intel® Stratix® 10 FPGA IP
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    Description

    The Intel® Stratix® 10 Mailbox Client IP may stop functioning or hang in the following scenarios :

    1. Attempting to issue a write command while the write FIFO register is empty

    2. Attempting to issue a write command while the write FIFO register has overflowed.

    3. Attempting to send a write before setting the chip select.

    Resolution

    If using Intel® Quartus® Prime Pro Edition Software version 19.1 and below, a power-cycle of the Intel® Stratix® 10 device is required to recover from this condition. 

    If using Intel® Quartus® Prime Pro Edition Software version 19.2 and above, scenario 1 and 2 can be recovered from by resetting the Intel® Stratix® 10 Serial Flash Mailbox Client IP. For scenario 3, an error message will be prompted if the device is configured with non ASx4 configuration scheme. However, QSPI_SET_CS command is optional if the device is configured with ASx4 configuration scheme.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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