Article ID: 000074661 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Verilog and VHDL simulation error in Riviera-PRO: "# ALOG: Error: VCP2120 Syntax error in ITF file for unit..."

Environment

  • Quartus® II Subscription Edition
  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When compiling Verilog and VHDL simulation scripts in the Aldec® Riviera-PRO™ Advanced Verification Platform, the following error occurs:

    # ALOG: Error: VCP2120 Syntax error in ITF file for unit 'sv_xcvr_pipe_native' in library 'altera_xcvr_pipe_0'. Please contact Aldec Support

    Please note this issue is a Riviera-PRO simulation bug and is not limited to the Altera® Transceiver PHY IP core.

    Resolution

    This issue is fixed in the Quartus® II software release version 13.1 and Aldec’s Riviera-PRO 2013.6.

    To workaround this issue in previous software versions, compile all IP simulation files (not Quartus II software files) with a single vlog command.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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