Critical Issue
When compiling Verilog and VHDL simulation scripts in the Aldec® Riviera-PRO™ Advanced Verification Platform, the following error occurs:
# ALOG: Error: VCP2120 Syntax error in ITF file for unit 'sv_xcvr_pipe_native'
in library 'altera_xcvr_pipe_0'. Please contact Aldec Support
Please note this issue is a Riviera-PRO simulation bug and is not limited to the Altera® Transceiver PHY IP core.
This issue is fixed in the Quartus® II software release version 13.1 and Aldec’s Riviera-PRO 2013.6.
To workaround this issue in previous software versions, compile
all IP simulation files (not Quartus II software files) with a single vlog
command.