Article ID: 000074647 Content Type: Troubleshooting Last Reviewed: 06/18/2012

Deep Power Down Issue With LPDDR2 Interfaces on Cyclone V Devices


  • Quartus® II Subscription Edition

    Critical Issue


    This problem affects LPDDR2 products.

    In LPDDR2 interfaces targeting Cyclone V devices, if the auto power down mode is enabled, the HPC II memory controller cannot immediately issue a deep power down request in response to a user request to invoke deep power down mode. This situation occurs because the system is unable to exit the auto power down loop when a deep power down request occurs.

    When a deep power down request occurs, soft logic within the IP automatically triggers a self refresh, allowing the system to exit the auto power down mode and process the deep power down request after completion of the self refresh.


    This issue does not require a workaround. The purpose of this erratum is to explain the reason for the automatically generated self refresh, which is visible on the memory bus.

    This issue will not be fixed.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs