Article ID: 000074628 Content Type: Troubleshooting Last Reviewed: 02/12/2023

Why can't the Parallel Flash Loader II Intel® FPGA IP configure Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Design Software
  • MicroBlaster™ Fast Passive Parallel Software Driver
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Paraller Flash Loader II Intel® FPGA IP (PFLII IP) will first check if CONF_DONE is low. The IP will not proceed with configuration if it is already high. This is why the PFLII IP cannot configure Intel® Stratix® 10 devices.

    Resolution

    Check if CONF_DONE is pulled up as CONF_DONE and INIT_DONE  are no longer required to be pulled up to VCCIO_SDM.

    Note that SDMIO_0 and SDM_16 are initially pulled down. Hence an intermediate voltage level by pull-up and internal pull-down resister might cause configuration failure when using the PFLII IP.

    PFLII IP monitors CONF_DONE signal low as start condition of operation. This requirement has been changed for Intel® Stratix® 10 devices.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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