How to implement MIPI D-PHY solution with both High Speed (HS) and Low Speed Low Power (LP) TX Mode in a single lane?

For MIPI D-PHY implementation, you have to assign a differential I/O standard for High Speed (HS) TX pin and single-ended I/O standard for Low Power (LP) TX pin. High Speed (HS) pin needs to be tri-stated when Low Power (LP) TX pin is transmitting data.

However due to the differential I/O of High Speed (HS) TX pin cannot be tri-stated, you can apply 2 single-ended I/O standards in High Speed (HS) TX mode.

For instance, you may use 2 single-ended HSTL 1.8V instead of differential HSTL 1.8V for High Speed (HS) TX pin.