Article ID: 000074624 Content Type: Product Information & Documentation Last Reviewed: 12/05/2017

How to implement MIPI D-PHY solution with both High Speed (HS) and Low Speed Low Power (LP) TX Mode in a single lane?

Environment

  • Intel® Quartus® Prime Pro Edition
  • ASMI Parallel II Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    For MIPI D-PHY implementation, you have to assign a differential I/O standard for High Speed (HS) TX pin and single-ended I/O standard for Low Power (LP) TX pin. High Speed (HS) pin needs to be tri-stated when Low Power (LP) TX pin is transmitting data.

    However due to the differential I/O of High Speed (HS) TX pin cannot be tri-stated, you can apply 2 single-ended I/O standards in High Speed (HS) TX mode.

    For instance, you may use 2 single-ended HSTL 1.8V instead of differential HSTL 1.8V for High Speed (HS) TX pin. 

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    Cyclone® IV FPGAs