Yes. You need PLL reconfiguration if the VCO frequency exceeds the operating range, even when only the input reference clock frequency is changed. Still, the multiplication or division ratio needs to be changed.
For example, the IOPLL for Intel® Arria® 10 devices has a PLL VCO operating range from 600MHz to 1600MHz for -1 speed grade.
Here is an example set of parameters.
Input frequency = 25MHz
Output frequency = 25MHz
Pre-Scale Counter N = 1
Multiply Counter M = 24
Post-Scale Counter C = 24
VCO frequency = Input frequency * M/N = 25MHz * 24 = 600MHz
The total multiplication ratio is 1.
When you want to generate a 100MHz output clock from a 100MHz input clock, the total multiplication ratio is the same 1. But if you use the same PLL without changing the parameters and change the input frequency from 25MHz to 100MHz to get 100MHz output, the VCO frequency is 100MHz * 24 = 2400MHz and violates the maximum PLL VCO operating frequency of 1600MHz. So it would be best if you had PLL reconfiguration to change the parameters to meet the PLL VCO operating range.
You can find PLL Freq Min Lock and PLL Freq Max Lock in the PLL Usage Summary under the Fitter category of Compilation Report of Quartus® Prime software after compilation. They show the range of the input reference clock frequency of your PLL that doesn't exceed the VCO frequency operating range. When you change the input reference clock frequency beyond the range, you need to use PLL reconfiguration.
See the above description.