Critical Issue
Description
The DQS and DQSn signals generate an extra pulse after a write for designs that use the half-rate DDR or DDR2 SDRAM with HPC architecture.
Because the controller asserts the DM pin high after the write burst, the extra pulse does not cause any incorrect data to be written into the memory.
This issue affects all designs that use half-rate DDR or DDR2 SDRAM with HPC architecture and target Arria II GX, Stratix III, or Stratix IV devices.
If your board is not using DM pins, incorrect data may be written into the memory.
Resolution
Use the HPC II architecture instead.
This issue will be fixed in a future version of the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP.