During simulation of the PCI Express® core, it is recommended that you set test_in[0] = 1 to speed up simulation initialization. When simulation mode is set, through setting test_in[0] =1, in addition to the transceiver initialization process being accelerated, this mode also reduces various LTSSM timeout conditions.
In this mode, most of the PCIe® LTSSM 1ms values are translated to 1.6us in simulation time. For example, the 24ms timeout value of the Recovery.RcvrLock state is 38.4us in simulation time. Other timeout values that are further reduced are below:
Detect.Quiet
Hardware timeout: 12ms
Simulation timeout: 3.2us
Detect.Active
Hardware timeout: 12ms
Simulation timeout: 3.2us
Recovery.RcvrLock
Hardware timeout: 24ms
Simulation timeout: 12.8us
Additionally, in simulation mode, further reduction of simulation time is achieved by transmitting 32 TS Ordered Sets instead of the 1024 at Polling.Active and Recovery.Rcvrlock LTSSM states.