Critical Issue
Description
The Altera® Conduit bus functional model (BFM) and Tri-State Conduit BFM do not generate a VHDL simulation model when the mixed simulation language option is selected. Simulations fail at the elaboration stage with the following error message:
Error: (vsim-3059) Cannot connect a VHDL array signal
to Verilog scalar port 'sig_fixedclk_locked'.
Resolution
If possible, you should disable the mixed simulation language option. Alternatively, you can edit the generated BFM signal declaration to use a bus signal type.