Article ID: 000074577 Content Type: Troubleshooting Last Reviewed: 02/14/2023

Why am I not able to read the correct RU_RECONFIG_TRIGGER_CONDITION register value even though an error has occurred during remote system update in Cyclone® IV devices?



When you are reading the RU_RECONFIG_TRIGGER_CONDITION register in Cyclone® IV devices at the address offset 0x18 in factory image mode, you might get the value 0x0 even though an error has occurred during application image update.

According to the Remote Update Intel® FPGA IP User Guide under Table 20, the last two bits of the address offset represents the read_source signals. Thus, the address offset 0x18 last two bits is 00 which refers to current state contents in status register. This is the reason why you will see the RU_RECONFIG_TRIGGER_CONDITION register value 0x0 when reading at the address offset 0x18.



You have to write the correct address offset to carry read_source value as shown in Table 21 of the Remote Update Intel FPGA IP User Guide. In Cyclone IV devices, you can only read the reconfiguration trigger condition during read_source = 01 (Read Past Status 1 reconfiguration trigger condition source) and read_source = 10 (Read Past Status 2 reconfiguration trigger condition source). Thus, you can read the RU_RECONFIG_TRIGGER_CONDITION register either at address offset 0x19 (read_source=01) or 0x1A (read_source=10). 

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Cyclone® IV FPGAs



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