Article ID: 000074564 Content Type: Troubleshooting Last Reviewed: 03/11/2019

What is the maximum supported frequency of the input clock in the Mailbox Client Intel® Stratix® 10 FPGA IP Core?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The maximum supported frequency of the input clock in the Mailbox Client Intel® Stratix® 10 FPGA IP Core is 250 MHz.

    Please note that the actual allowable maximum frequency depends on user design.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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