Article ID: 000074551 Content Type: Error Messages Last Reviewed: 10/03/2012

Warning (*): Ignored filter: sv_reconfig_pma_testbus_clk could not be matched with a clock

Environment

  • Stratix® V GS FPGA
  • Stratix® IV GX FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to  a problem in the Quartus® II software version 12.0sp2 and earlier, you may see this warning during fitting (place & route) if your design has multiple Altera® transceiver Reconfiguration Controllers.

    Resolution

    To workaround this issue, add new "create_generated_clock" constraints for each of the transceiver Reconfiguration Controllers’ ignored "sv_reconfig_pma_testbus_clk" constraints. The new constraints should be added to the user SDC file. The following is an example for two reconfiguration controllers named INST_A and INST_B.

    create_generated_clock -name sv_reconfig_pma_testbus_clk_A -source [get_pins -compatibility_mode -no_duplicates INST_A*|basic|s5|reg_init[0]|clk] -divide_by 1  [get_registers INST_A*sv_xcvr_reconfig_basic:s5|*alt_xcvr_arbiter:pif*|*grant*]

    create_generated_clock -name sv_reconfig_pma_testbus_clk_B -source [get_pins -compatibility_mode -no_duplicates INST_B*|basic|s5|reg_init[0]|clk] -divide_by 1  [get_registers INST_B*sv_xcvr_reconfig_basic:s5|*alt_xcvr_arbiter:pif*|*grant*]

    This issue is scheduled to be fixed in a future version of the Quartus II software.

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