The following two conditions may cause SOPC Builder (SOPCB) to break the user burst access into single dword accesses on PCIe® bus.
1. If the datapath width of user design does not match with the Avalon®-MM width of PCIe core, SOPCB automatically inserts adapters to match them up. As a result, user burst access will be broken into multiple dword accesses.
2. If the application layer is not configured to use pcie_core_clk generated from the PCIe core,
SOPCB will insert asynchronous logic to break the current burst access to single dword accesses.
To workaround this issue, the user logic must implement the following requirements:
1. The application datapath width is the same as the Avalon-MM width of PCIe core.
2. All user clocks are connected to pcie_core_clk.
3. "Use PCIe core clock" is selected in "Avalon Clock Domain" under "Avalon" tab in PCIe GUI.