Article ID: 000074530 Content Type: Error Messages Last Reviewed: 12/08/2017

Error: RST_N port on the PLL is not properly connected on instance

Environment

    Intel® Quartus® Prime Standard Edition
    Intel® Quartus® Prime Pro Edition
    IOPLL Intel® FPGA IP
    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

While compiling in Intel® Quartus® Prime software, you may see this error in the synthesis stage if an IOPLL instance in an Intel Arria® 10 or Stratix® 10 design is not connected to a valid reset signal.

 

Resolution

The reset port of the IOPLL needs to be driven either by an external input pin or internally generated logic so that the IOPLL can be reset if it loses lock. 

Related Products

This article applies to 2 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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