Article ID: 000074492 Content Type: Troubleshooting Last Reviewed: 05/06/2016

Does the Hard IP for PCI Express for the Avalon-MM interface with DMA support out of order completions?

Environment

    Quartus® II Subscription Edition
    DMA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description When the Hard IP for PCI Express® read DMA module receives out-of-order completions, the DMA can, in certain instances, flag the descriptor completion signal too early, before all outstanding transactions are completed.
Resolution This issue will be fixed in a future version of the Quartus® II software.

Related Products

This article applies to 5 products

Stratix® V GT FPGA
Arria® V GZ FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GX FPGA

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