Article ID: 000074481 Content Type: Troubleshooting Last Reviewed: 09/11/2012

When reconfiguring a transceiver channel to switch between CMU PLL within the transceiver block to an additional CMU PLL or ATX PLL outside the transceiver block in Stratix IV GX device, why does the transceiver block create incorrect tx_clkout frequency

Environment

  • Stratix® IV GT FPGA
  • Stratix® IV GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

 

Intel has identified an issue in functional simulation and hardware for Stratix® IV devices when using Multi-PLL dynamic reconfiguration feature. This Multi-PLL feature enables you to reconfigure a transceiver channel to listen to additional transmitter PLLs located outside the transceiver block.

When you use this feature in functional simulation you may observe that when you switch from a transmitter PLL within the transceiver block to a transmitter PLL (CMU/ATX) outside the transceiver block, the tx_clkout frequency is incorrect. In hardware, Quartus® II Software does not merge transmitter PLLs between multiple instances as expected.

This issue is further explained with the following example: Consider a design with the following requirements

  • One channel (A shown in the figure) running at OTU1 data rate (2.666 Gbps)
  • One channel (B shown in the figure) capable of switching between OTU1, Fibre Channel 4G (4.25G), and SONET OC48 (2.488 Gbps)
  • Assume that the above two channels need to placed in two different transceiver blocks.

To implement this design, you must instantiate two ALTGX instances as shown below and use the Multi PLL reconfiguration feature (Option - "Use additional CMU/ATX PLL..." in the reconfiguration settings screen of the ALTGX Megawizard™)

  • ALTGX Instance 1: has Channel A, Main PLL as PLL2 running at 2666 Mbps.
  • ALTGX Instance 2: has Channel B, Main PLL as PLL0 (0 is the logical reference index of the PLL) running at 4250 Mbps, Additional PLLs as PLL1 running at 2488.32 Mbps and PLL2 running at 2666 Mbps

In both the ALTGX instances, keep the same number of input reference clocks. This is required to share PLL2 between the two instances as described in step3 below.

For this design configuration, only three PLLs are required to achieve this, as shown in Figure 1:

Figure 1.Multi PLL Reconfiguration Example Design Scenario

Figure 1
View full size

 

Issue in functional simulation:

In functional simulation when you switch from PLL0 to PLL2 using the 'Channel reconfiguration with TX PLL select' mode you will find that the tx_clkout frequency is incorrect. The following are the workarounds

If CMU PLL is the 'outside transceiver block PLL' :

- Perform TX PLL reconfiguration on the ‘outside transceiver block PLL’ ( PLL2) and THEN

- Perform ‘Channel and TX PLL select’ on the desired channel (Channel B) to switch to this ‘outside transceiver block PLL’

 

If ATX PLL is the 'outside transceiver block PLL' :

 

 

- Reconfiguration is not supported for ATX PLL.

- Therefore make ATX PLL (PLL2) as your main PLL (default PLL that the channel listens to) and then

- Switch to the CMU PLL (PLL0) within the transceiver block and back.

Issue in hardware

The QII software does not merge the PLL2 between the two instances which is incorrect.

To merge the PLL2 of both the ALTGX instances into one physical transmitter PLL location,perform the following steps

1) Create a GXB TX PLL Reconfiguration group setting in the assignment editor and assign the same value (example: 0 or 1, 2,etc) for the tx_dataout of both instances

2) Manually assign location of the TX PLL that provides clocks to channels outside its transceiver block. In this example it is PLL2. The steps below show the manual location assignment method.

  • Select the GXB Transmitter PLL from the Resource Section of the Fitter option in the Compilation Report. You can see the transmitter PLL node information for all the PLLs used in the design.
  • For the PLL2, you can see two location assignments for the same node (example:tx_pll_edge0)
  • Use one of the two locations for tx_pll_edge0 and manually assign it in the assignment editor as shown in Figure 2

Figure 2.Manual Assignment of Transmitter PLL

Figure 1
View full size

 

For information on the physical location of the PLL associated with the x, y coordinate, refer to AN578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices

3) Make the 'txplledge<x>.inclk<>' parameters identical in the ALTGX instances by modifying the wrapper file.

For this example scenario, the Instance 2 wrapper file will show the following parameters

 tx_pll_edge0.inclk0_input_period = 9412,

tx_pll_edge0.inclk1_input_period = 6430,

tx_pll_edge0.inclk2_input_period = 6002,

 

The Instance 1 wrapper file will show the following parameters

tx_pll_edge0.inclk0_input_period = 0,

tx_pll_edge0.inclk1_input_period = 0,

tx_pll_edge0.inclk2_input_period = 6002,

 

 

The QII software cannot merge PLL2 of both instances, when there is a mismatch between the input reference clock parameter (INCLK INPUT PERIOD)

 

 

Therefore specify the tx_pll_edge<>. parameters  from instance2 that has the maximum number of PLLs and include it in the wrapper for instance1. The following is the change required in instance1

tx_pll_edge0.inclk0_input_period = 9412,

tx_pll_edge0.inclk1_input_period = 6430,

tx_pll_edge0.inclk2_input_period = 6002,

 

 

 

3) Compile the design and observe the GXB Transmitter PLL from the Resource Section of the Fitter option in the Compilation Report

 

 

 

 

You can now see that the transmitter PLLs from the two instances have been merged into a single physical location ( example:HSSIPLL_X119_Y10_N135)

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.