Article ID: 000074479 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How should I connect unused Rup pins on my FPGA?



Altera® FPGAs that support calibrated on chip termination (OCT) have Rup and Rdn pins which connect to external precision resistors for the calibrated OCT circuitry.  When calibrated OCT is not used, the Rup and Rdn pins are available as user I/O.  If they are not used in the design, then the Rup pins can be tied to either the VCCIO of bank in which they reside, or to GND.  Unused Rdn pins should be tied to GND.   

The Quartus® II design software pinout file will recommend connecting unused Rup pins to GND.  Some device Pin Connection Guidelines will recommend connecting unused Rup pins to the VCCIO of the bank in which they reside.  You can choose to connect unused Rup pins to either the VCCIO of the bank in which the Rup pins reside or to GND depending on what is more convenient for your PCB design. 

The Pin Connection Guidelines for the different device families will be updated to include both VCCIO and GND connections as options for unused Rup pins. 

Related Products

This article applies to 4 products

Arria® GX FPGA
Cyclone® III FPGAs
Stratix® III FPGAs
Stratix® II GX FPGA