Article ID: 000074473 Content Type: Troubleshooting Last Reviewed: 07/24/2015

MGL_INTERNAL_ERROR: Port object altpll_avalon|altpll inst sd1|phasecounterselect of width 3 is being assigned the port altpll_avalon|w_phasectrsel of width 4 which is illegal, as port widths dont match nor are multiples.

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to an issue in Quartus® II software version 15.0 and earlier, you will get this error if an ALTPLL is generated in QSYS with the Dynamic Phase Stepping feature enabled, when targeting a MAX® 10 device.

    Resolution

    If using Dynamic Phase Stepping, implement the ALTPLL outside of QSYS to avoid getting this error.

    This issue is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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