Article ID: 000074452 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get the Error:"Can't place fast or enhanced PLL pll#:inst# in selected device due to device constraints" during compilation in the Quartus® II software?


  • PLL
    Description You might get the error if you have mixed IO standards on the input and output clocks from the PLL. For example, you will get this error during compilation if you assign a Differential IO standard assignment on the input clock to the PLL, while the output clock is assigned a single-ended IO standard.

    In order to maintain an acceptable noise level on the VCCIO supply, the Quartus®  II software enforces restrictions on placement of single-ended I/O pads in relation to differential pads. Use the following guidelines for placing single-ended pads with respect to differential pads in Stratix® /Stratix GX and Cyclone®  devices.

    1. Single-ended inputs may be only be placed four or more pads away from a differential pad.
    2. Single-ended outputs and bidirectional pads may only be placed five or more pads away from a differential pad.

    The Quartus II software generates the error message for illegally placed pads.

    Note: Altera®  might relax this restriction in the future, pending silicon characterization. Please contact Altera Applications for more information.

    Related Products

    This article applies to 3 products

    Stratix® GX FPGA
    Cyclone® FPGAs
    Stratix® FPGAs



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