Article ID: 000074434 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why are certain input clock frequency options not listed in the ALT2GXB MegaWizard Plug-In-Manager in the Quartus II software versions 7.1 SP1, 7.2, or 7.2 SP1?


  • Quartus® II Subscription Edition

    In the Quartus® II software versions 7.1 SP1, 7.2, and 7.2 SP1, the ALT2GXB MegaWizard Plug-In does not list certain input clock frequencies when you select specific Data rate division factor values on the General page. For example, the input clock frequency 106.25 MHz is not listed when you select a 4250 Mbps data rate with data rate division factor of 4. In version 7.1, the 106.25 MHz frequency was listed.

    The megafunction restricts certain frequencies because the phase frequency detectors (PFD) in each Stratix® II GX TXPLL and RXPLL require a minimum input reference clock frequency of 50 MHz. Until the Quartus II software version 7.1, the ALT2GXB wizard included input clock frequencies for specific data rate division factor values that seem to violate the PFD limit for RX PLL. For example, for a data rate of 4250 Mbps and a data rate division factor of 4, the input clock frequency value of 106.25 MHz .seems to violate the input clock frequency minimum of 50 MHz for the PFD in the RXPLL because the 106.25 MHz data rate is divided by 4 before it is provided to the PFD. However, in this case, the Quartus II software fitter modifies the multiplier and divider values of the RXPLL and selects appropriate values so that the 50 MHz minimum frequency is met at the input of the PFD. The Quartus II software versions 7.1 SP1, 7.2, and 7.2 SP1 incorrectly restrict these types of input clock frequency values in the wizard. The 106.25 MHz setting is a valid setting for the input clock frequency in this case.


    To work around this restriction in the versions 7.1 SP1, 7.2, or 7.2 SP1, follow these steps:

    1. In the MegaWizard Plug-In Manager for the ALT2GXB megafunction, select any value listed in the What is the input clock frequency? list.
    2. Complete the wizard  to generate the cusomized megafunction instantiation wrapper file.
    3. Modify the following parameter in the generated wrapper file to change the input clock frequency to a value allowed in the Quartus II software version 7.1.
      • For TX-only configuration: 
      • For RX-only configuration:
      • For full duplex configuration configuration:
        alt2gxb_component.cmu_pll_inclock_period and alt2gxb_component.rx_cru_inclock_period

      These parameters are specified in time period (in ps). Convert a valid input frequency value (one that was allowed in version 7.1) to a time period in ps.

      For example: To set 106.25 MHz for a 4250 Mbps data rate with the Data rate division factor of 4 for full duplex configuration, set the following:

      alt2gxb_component.cmu_pll_inclock_period = 9412
      alt2gxb_component.rx_cru_inclock_period = 9412

      (Note that 9412 ps = 1/106.25MHz)

    4. Compile the design using the modified wrapper file.

    To simulate the design, generate simulation netlist files using the Quartus II software. To generate a netlist for functional simulation, follow these steps:

    1. On the Assignments menu, choose Settings.
    2. Under EDA Tool Settings, choose Simulation.
    3. Select the Tool name for your third-party simulation tool.
    4. In the Format for output netlist list, select VHDL or Verilog based on your requirements.
    5. In the Output directory field, specify the directory for the .vo or .vho file.
    6. Click More Settings and set Generate netlist for functional simulation only to On.
    7. Compile the top-level module of your design that contains the alt2gxb (and any alt2gxb_reconfig instances if the alt2gxb_reconfig block is used in the design). 
      • Note: You must connect the reconfig_fromgxb and reconfig_togxb ports between the alt2gxb and the alt2gxb_reconfig instances. Otherwise, the Quartus II software removes these ports, and the generated .vo or .vho simulation model file does not work as expected.

    This problem has been fixed begining with the Quartus II software version 8.0.

    Related Products

    This article applies to 1 products

    Stratix® II GX FPGA



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