Due to a problem in the Quartus® II software versions 10.0 through 10.1 SP1, the tx_outclock signal generated by the ALTLVDS_TX megafunction does not toggle when using a serialization factor of 3. Instead, the tx_outclock signal sticks at 0. The SERDES block generated in these versions creates the tx_outclock signal incorrectly. You should disable the tx_outclock port in the ALTLVDS_TX megafunction when using a serialization factor of 3.
To work around this problem, generate an output clock by creating a second ALTLVDS_TX megafunction with a channel width of 1 and deserialization factor of 3. You can hard wire the data input ports to 1 and 0 to create an output clock. Connect the tx_inclock and optional reset signal to the same signals that are used for the existing ALTLVDS_TX megafunction in your design. The Quartus II software can share the same PLL for each ALTLVDS_TX megafunction when the same tx_inclock and reset signals are used. You must turn on Use shared PLL(s) for receivers and transmitters in both megafunctions. Typically with a serialization factor of 3, you should set tx_in[0] and tx_in[2] to 1, and set tx_in[1] to 0.
This problem is fixed beginning with the Quartus II software version 11.0.