Article ID: 000074416 Content Type: Troubleshooting Last Reviewed: 10/20/2017

Why do I see a timing warning related to alt_fi_reserved_intosc when using the Arria 10 SEU IP?


  • Intel® Quartus® Prime Pro Edition
  • Advanced SEU Detection Intel® FPGA IP
  • Error Message Register Unloader Intel® FPGA IP
  • CRC Error Verify Intel® FPGA IP

    When using the Error Message Register Unloader, Fault Injection and Altera Advanced SEU detection IP with Arria 10 devices, you may get an unconstrained clock named "alt_fi_reserved_intosc".

    While Arria 10 is useing EMR unloader IP and Fault Injection IP, in which the clk signal in EMR unloader IP is from the intocs output of Fault Injection IP. In this case, EMR unloader IP hasn't generate correctly the .sdc file for timing constraint.

    The main reason for this warning is that the state machine in EMR unloader IP is not correctly constrained as a clock.



    2. Then constrain the state machine as follows:

        create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_nets {<user clock>}] [get_keepers {*altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH}]

            - Here the clock name can be modified based on your design, and <user clock> is the same as Step 1.

            - Generally the name get_keepers is shown as above, we'd also recommend to verify this in TimeQuest.

    To work around this issue, modify the .sdc file to meet the constraint requirement for intosc, as shown below:

    1. Modify the create_clock to:

        create_clock -period "50 MHz" -name intosc [get_nets {<user clock>}]

            - Because intosc is generated by internal oscillator, get_nets is needed to constrain the signal node of intosc.

            - For your reference, the <user clock> for intosc is generally named as:  {*|alt_fault_injection_component|alt_fi_inst|intosc}


    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs