Article ID: 000074414 Content Type: Troubleshooting Last Reviewed: 09/24/2017

Why does SCFIFO almost_empty signal stay high while usedw is larger than almost_empty threshold ?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the SCFIFO, the almost_empty signal stays "high" even if enough data is written into SCFIFO.

This problem only occurs in case of both "Show-ahead mode" used and almost_empty threshold is set to "2".

Resolution

To work around this issue, perform one of the following actions:

  • Set Normal synchronous FIFO mode instead of Show-ahead synchronous FIFO mode
  • Set the almost empty value to something other than 2
  • Enable underflow circuitry protection

This problem is fixed beginning with the Quartus Prime software version 17.1.

Related Products

This article applies to 6 products

Arria® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs
Cyclone® IV FPGAs
Stratix® V FPGAs
Stratix® IV FPGAs

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.