Error (10170): Verilog HDL syntax error at <location> near text "generate"; expecting "end", or an identifier ("generate" is a reserved keyword ), or a sequential statement

You may get this error if your design uses extra generate/endgenerate statements for nested loops. Older versions of the Quartus® II software erroneously accepted nested generate/endgenerate statements in Verilog HDL design files. The Quartus II software beginning with version 6.0 correctly flags nested generate/endgenerate statements as an error.

If you have loops within a loop, you only need one generate/endgenerate pair, as shown in the following example that reverses the bits in a bus.

genvar i,j;
generate
for( i=0; i<8; i=i 1 )
begin : outer
    for (j=0;  j<8; j=j 1 )
        begin : inner
        assign data_out[i][j] = data_in[7-i][7-j]; 
    end
end
endgenerate