Article ID: 000074360 Content Type: Troubleshooting Last Reviewed: 03/05/2018

Incorrect formula in CRC calculation Time of Cyclone V Device Handbook Volume 1

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Issue 540455 : Chapter 7 SEU Mitigation for Cyclone® V, section Devices CRC Calculation Time For Entire Device, Cyclone V Device Handbook Volume 1: Device Interfaces and Integration version 2018.03.02

It says as follows:

Minimum time (n) = 2^n * tMIN

But this is incorrect.  It should be as follows:

Minimum time (n) = 2^n / Minimum divisor setting * tMIN

For example, 9ms of tMIN in Cyclone V E A2 device is the minimum time for divisor setting of 2 or n=1.  When calculating the minimum time for divisor setting of 4 or n=2, the formula is as follows:

2^2/2*9=4/2*9=2*9=18 (ms)

Related Products

This article applies to 1 products

Cyclone® V FPGAs and SoC FPGAs

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.