Critical Issue
By default, scrambling/descrambling is turned on in the RapidIO
II IP core. That is, the default value of the Scrambling/descrambling
enabled
bit of the LP-Serial Lane n Status 4
register
at offset 0x220 (and offsets 0x240, 0x260, and 0x280, depending
on the number of lanes in your RapidIO II IP core variation) is
1’b1.
However, the RapidIO II MegaCore Function v12.1 SP1 User Guide erroneously indicates in Table 6-21 that the default value is 1’b0.
Be aware that by default, scrambling/descrambling is turned on in the RapidIO II IP core.
This issue is fixed in version 14.0 of the RapidIO II MegaCore Function User Guide.