Article ID: 000074340 Content Type: Troubleshooting Last Reviewed: 10/17/2011

A CDR locked signal might not be stable when using serial loopback mode when simulating a Custom PHY IP for Stratix V

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When you simulate a Custom PHY IP, a CDR locked signal might not be stable when using serial loopback mode.

    Resolution

    Disable serial loopback mode and use an external serial loopback in the testbench.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs