Article ID: 000074340 Content Type: Troubleshooting Last Reviewed: 10/17/2011

A CDR locked signal might not be stable when using serial loopback mode when simulating a Custom PHY IP for Stratix V

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 10.0.1

FPGA Intellectual Property

Simulation

Version Found: 10.0.1

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

When you simulate a Custom PHY IP, a CDR locked signal might not be stable when using serial loopback mode.

Resolution

Disable serial loopback mode and use an external serial loopback in the testbench.

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