Article ID: 000074298 Content Type: Troubleshooting Last Reviewed: 09/14/2011

Reduced Clock Rate Specification for Column and Row I/Os


  • Quartus® II Subscription Edition

    Critical Issue


    Commencing with the Quartus. II software version 10.0 SP1, the clock rate specification for column and row I/Os is decreased from 150MHz to 133MHz for full-rate DDR2 IP cores on Cyclone IV E I8L devices with vcc=1.0V. This reduction in specification is due to changes associated with finalized timing models.

    This issue affects all configurations.

    The maximum clock rate for column and row I/Os is decreased.


    Do not use the IP core with column and row I/Os greater than 133MHz in full-rate mode on Cyclone IV E I8L devices with vcc=1.0V.

    Designs already using Cyclone IV E I8L devices with vcc=1.0V with full-rate DDR2 SDRAM at 150MHz (the previous clock rate specification) which pass timing in the Quartus II software version 10.0SP1 and later should continue to work, as long as you accurately populate the Board Settings panel in the MegaWizard and you correctly enter board trace models representative of the system in the Pin Planner.

    This issue will not be fixed.

    Related Products

    This article applies to 1 products

    Cyclone® IV FPGAs